library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity alucontrol is
	port(
		output	: out	std_logic_vector(2 downto 0);
		aluOp	: in	std_logic_vector(1 downto 0);
		funct	: in	std_logic_vector(5 downto 0)
	);
end alucontrol;

architecture alucontrol_arch of alucontrol is

begin

	process(aluOp) begin

		case aluOp is
			when "10" =>
				case funct is
					when "100000" => output <= "010"; -- ADD
					when "100010" => output <= "110"; -- SUB
					when "100100" => output <= "000"; -- AND
					when "100101" => output <= "001"; -- OR
					when "101010" => output <= "111"; -- SLT
					when others => output <= "000";
				end case;
			when "00" => output <= "010"; -- LW, SW
			when "01" => output <= "110"; -- BEQ
			when "11" => output <= "100"; -- LUI
			when others => output <= "000";
		end case;

	end process;

end alucontrol_arch;
